FEC for Ethernet: A New Path to Flexibility

FEC diagram

The IEEE’s task force on 200/400 Gigabit Ethernet is preparing to issue a standard that specifies a single Forward Error Correction code, Reed-Solon (544,514, 10), based on the use of PAM4 line coding. This might appear to be a limiting factor for FEC implementations of the future, except that the group also has proposed a new sublayer that allows flexible use of end-to-end FEC or segment-by-segment FEC without underlying changes to Ethernet’s PHY or MAC layers.

For the first time in Ethernet’s history, developers can experiment with proprietary FEC while retaining compatibility with Ethernet standards. The “extender sublayer,” or CDXS, sits between the media-independent interface (MII) and physical attachment unit interface (AUI), giving hardware designers more freedom to experiment with error-correcting codes. The test community must be cognizant of how this could change future network emulation, however.

Learn more about FEC and how Spirent’s 400/200/100/50GbE quad speed-test modules were first to market, and have been designed to support the mandatory FEC/PCS  IEEE requirements.

In this paper, the following topics will be discussed:

  • FEC’s Belated Relevance to Ethernet
  • Extenders for FEC Flexibility
  • Test and Emulation in a CDXS and FEC Environment
     

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